329 lines
10 KiB
C
329 lines
10 KiB
C
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#include <stdint.h>
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#include <string.h>
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#include "osi_api.h"
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#include "ql_api_osi.h"
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#include "ql_api_spi.h"
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#include "osi_compiler.h"
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//#include "cfg.h"
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#include "../EC600U_t2n/include/t2n.h"
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#include "ql_log.h"
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#define AC_CURRENT_REG_ADDR 24
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#define ENC_VALUE_REG_ADDR 28
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// #define LOGD(msg, ...) QL_LOG(QL_LOG_LEVEL_DEBUG, "bl0939", msg, ##__VA_ARGS__)
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// #define LOGI(msg, ...) QL_LOG(QL_LOG_LEVEL_INFO, "bl0939", msg, ##__VA_ARGS__)
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// #define LOGW(msg, ...) QL_LOG(QL_LOG_LEVEL_WARN, "bl0939", msg, ##__VA_ARGS__)
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// #define LOGE(msg, ...) QL_LOG(QL_LOG_LEVEL_ERROR, "bl0939", msg, ##__VA_ARGS__)
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#define LOGD(msg, ...) QL_LOG(QL_LOG_LEVEL_VERBOSE, "bl0939", msg, ##__VA_ARGS__)
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#define LOGI(msg, ...) QL_LOG(QL_LOG_LEVEL_VERBOSE, "bl0939", msg, ##__VA_ARGS__)
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#define LOGW(msg, ...) QL_LOG(QL_LOG_LEVEL_WARN, "bl0939", msg, ##__VA_ARGS__)
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#define LOGE(msg, ...) QL_LOG(QL_LOG_LEVEL_ERROR, "bl0939", msg, ##__VA_ARGS__)
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extern int enc_value;
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// static ql_task_t *current_task_handle = NULL;
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#define BL0939_READ_TIMER 0x8000
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osiThread_t *bl_thread_handle = NULL;
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osiTimer_t *bl_timer = NULL;
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static int spi_wait_write_read = 0;
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ql_sem_t spi_write_semaphore;
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ql_sem_t spi_read_semaphore;
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#define QL_SPI_WAIT_NONE 0
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#define QL_SPI_WAIT_WRITE 1
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#define QL_SPI_WAIT_READ 2
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extern uint16_t gWordVar[];
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static const uint8_t bl0939_cmd[36] =
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{
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0x55, 0x00, 0, 0, 0, 0,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0x55, 0x07, 0, 0, 0, 0,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0x55, 0x06, 0, 0, 0, 0};
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static uint8_t spi_txbuf[36] OSI_CACHE_LINE_ALIGNED;
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static uint8_t spi_rxbuf[36] OSI_CACHE_LINE_ALIGNED;
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static void spi_cb_handler(ql_spi_irq_s cause)
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{
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if (cause.rx_dma_done == 1 && spi_wait_write_read == QL_SPI_WAIT_READ)
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{
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spi_wait_write_read = 0;
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ql_rtos_semaphore_release(spi_read_semaphore);
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}
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if (cause.tx_dma_done == 1 && spi_wait_write_read == QL_SPI_WAIT_WRITE)
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{
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spi_wait_write_read = 0;
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ql_rtos_semaphore_release(spi_write_semaphore);
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}
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LOGD("spi_cb_handler rx_dma_done=%d tx_dma_done=%d\r\n", cause.rx_dma_done, cause.tx_dma_done);
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}
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static int spi_write(int fd, uint8_t *inbuf, int len)
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{
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int ret;
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spi_wait_write_read = QL_SPI_WAIT_WRITE;
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ql_spi_request_sys_clk(fd);
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ret = ql_spi_write(fd, inbuf, len);
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ql_rtos_semaphore_wait(spi_write_semaphore, 10);
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LOGD("spi_write inbuf=%p,len=%d,ret=%d", inbuf, len, ret);
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return ret;
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}
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static int spi_write_read(int fd, uint8_t *outbuf, uint8_t *inbuf, int len)
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{
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int ret;
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spi_wait_write_read = QL_SPI_WAIT_READ;
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ret = ql_spi_write_read(fd, inbuf, outbuf, len);
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ql_rtos_semaphore_wait(spi_read_semaphore, 10);
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LOGD("spi_write_read inbuf=%p,outbuf=%p,len=%d,ret=%d", inbuf, outbuf, len, ret);
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return ret;
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}
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static int check_sum_ch(uint8_t *resp, uint8_t *cmd, int offset)
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{
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uint8_t sum = ~(0x55 + cmd[offset - 1] + resp[offset] + resp[offset + 1] + resp[offset + 2]);
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if (resp[offset + 3] == sum)
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{
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return 1;
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}
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return 0;
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}
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uint32_t readUint24LE(uint8_t *buf, int offset)
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{
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return buf[offset] | buf[offset + 1] << 8 | buf[offset + 2] << 16;
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}
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uint32_t readUint24BE(uint8_t *buf, int offset)
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{
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return buf[offset] << 16 | buf[offset + 1] << 8 | buf[offset + 2];
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}
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float ac_current_coef[3] = {
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1.218f / (324004.f * 0.225 * 1000 / 2000) * 100.f,
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1.218f / (324004.f * 0.23 * 1000 / 2000) * 100.f,
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1.218f / (79931.f * 0.002 * 500) * 100.f};
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// uint8_t bl0939_rxbuf[36];
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int32_t ac_ad_values[3] = {0};
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static void bl_read_data_timer(void *parm)
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{
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osiTimerStart(bl_timer, 20);
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ql_event_t event;
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event.id = BL0939_READ_TIMER;
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if (bl_thread_handle)
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{
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ql_rtos_event_send(bl_thread_handle, &event);
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}
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// LOGD("bl_read_data_timer\r\n");
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}
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static uint32_t bl0939_read_reg(int fd, uint8_t reg)
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{
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spi_txbuf[0] = 0x55;
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spi_txbuf[1] = reg;
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spi_txbuf[2] = 0;
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spi_txbuf[3] = 0;
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spi_txbuf[4] = 0;
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spi_txbuf[5] = 0;
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// bl0939_spi_reset();
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spi_write_read(fd, spi_txbuf, spi_rxbuf, 6);
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spi_wait_write_read = QL_SPI_WAIT_READ;
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ql_rtos_semaphore_wait(spi_read_semaphore, 10);
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if (spi_rxbuf[5] == (uint8_t) ~(0x55 + reg + spi_rxbuf[2] + spi_rxbuf[3] + spi_rxbuf[4]))
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{
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return (uint32_t)spi_rxbuf[2] << 16 |
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(uint32_t)spi_rxbuf[3] << 8 |
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(uint32_t)spi_rxbuf[4] << 0;
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}
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return 0;
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}
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void bl0939_spi_reset(int fd)
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{
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spi_txbuf[0] = 0xff;
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spi_txbuf[1] = 0xff;
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spi_txbuf[2] = 0xff;
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spi_txbuf[3] = 0xff;
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spi_txbuf[4] = 0xff;
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spi_txbuf[5] = 0xff;
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spi_write(fd, spi_txbuf, 6);
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}
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uint32_t r_temp = 0;
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static int bl0939_write_reg(int fd, uint8_t reg, uint32_t val, int check)
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{
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int try_times = 0;
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uint8_t h = val >> 16;
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uint8_t m = val >> 8;
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uint8_t l = val >> 0;
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do
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{
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// bl0939_spi_reset();
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spi_txbuf[0] = 0xA5;
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spi_txbuf[1] = reg;
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spi_txbuf[2] = h;
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spi_txbuf[3] = m;
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spi_txbuf[4] = l;
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spi_txbuf[5] = ~(0XA5 + reg + h + m + l);
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spi_write_read(fd, spi_txbuf, spi_rxbuf, 6);
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ql_rtos_semaphore_wait(spi_read_semaphore, 10);
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if (0 == check)
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return 0;
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r_temp = bl0939_read_reg(fd, reg);
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if (r_temp == val)
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return 0;
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ql_rtos_task_sleep_ms(100);
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} while (try_times++ < 5);
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return 1;
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}
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void bl0939_init(int fd)
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{
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bl0939_spi_reset(fd);
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bl0939_write_reg(fd, 0x19, 0x005a5a5a, 0); // <20><>λ<EFBFBD>û<EFBFBD><C3BB>Ĵ<EFBFBD><C4B4><EFBFBD>
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bl0939_write_reg(fd, 0x1a, 0x00000055, 1); // <20><><EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD>
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bl0939_write_reg(fd, 0x10, 0xffff, 0); // Threshold A
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bl0939_write_reg(fd, 0x1E, 0xffff, 1); // Threshold B
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bl0939_write_reg(fd, 0x18, 0x00002000, 1); // cf
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bl0939_write_reg(fd, 0x1B, 0x000047ff, 0); // cf
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bl0939_write_reg(fd, 0x1a, 0x00000000, 1); // д<><D0B4><EFBFBD><EFBFBD>
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}
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void bl0939_task(void *data)
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{
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int ret;
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ql_spi_config_s spi_config = {0};
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int spi_no = QL_SPI_PORT1;
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spi_config.port = spi_no;
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spi_config.spiclk = QL_SPI_CLK_781_25KHZ;
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spi_config.framesize = 8;
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spi_config.input_mode = QL_SPI_INPUT_TRUE;
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spi_config.cs_polarity0 = QL_SPI_CS_ACTIVE_LOW;
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spi_config.cs_polarity1 = QL_SPI_CS_ACTIVE_LOW;
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spi_config.cpol = QL_SPI_CPOL_LOW;
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spi_config.cpha = QL_SPI_CPHA_2Edge; // mode 1
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spi_config.input_sel = QL_SPI_DI_1;
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spi_config.transmode = QL_SPI_DMA_IRQ;
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spi_config.cs = QL_SPI_CS0;
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spi_config.clk_delay = QL_SPI_CLK_DELAY_0;
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LOGD("bl0939_task entry");
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ql_rtos_task_sleep_ms(5000);
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ql_spi_init_ext(spi_config);
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ql_spi_cs_auto(spi_no);
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// uint32_t addr = (uint32_t)__spi_dma_out_buf;
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// addr += 32 - addr % 32;
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// spi_txbuf = (uint8_t *)(addr);
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// LOGD("spi_txbuf=%p",spi_txbuf);
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// addr = (uint32_t)__spi_dma_in_buf;
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// addr += 32 - addr % 32;
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// spi_rxbuf = (uint8_t *)(addr);
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// LOGD("spi_rxbuf=%p", spi_rxbuf);
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LOGD("ql_spi_init done");
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ql_rtos_semaphore_create(&spi_read_semaphore, 0);
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ql_rtos_semaphore_create(&spi_write_semaphore, 0);
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LOGD("semaphore create done");
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ql_spi_irq_s mask = {
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.rx_dma_done = 1,
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.tx_dma_done = 1,
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};
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ql_spi_set_irq(spi_no, mask, spi_cb_handler);
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LOGD("ql_spi_set_irq done");
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bl0939_init(spi_no);
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bl_thread_handle = osiThreadCurrent();
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bl_timer = osiTimerCreate(bl_thread_handle, bl_read_data_timer, (void *)spi_no); // 创建定时器
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if (NULL == bl_timer)
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{
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LOGE("bl_timer create failed\n");
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osiThreadExit();
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}
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ret = osiTimerStart(bl_timer, 20);
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if (ret)
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{
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LOGE("osiTimerStart failed ret=%d\n", ret);
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}
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LOGD("bl0939_task init done");
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ret = ql_pin_set_func(95, 5); // set pin 95 to gpio10
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if (ret != QL_GPIO_SUCCESS)
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{
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LOGE("ql_pin_set_func 95 err ret=%d", ret);
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}
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ql_gpio_set_direction(GPIO_10, GPIO_INPUT);
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ret = ql_pin_set_func(98, 5); // set pin 95 to gpio9
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if (ret != QL_GPIO_SUCCESS)
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{
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LOGE("ql_pin_set_func 98 err ret=%d", ret);
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}
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ql_gpio_set_direction(GPIO_9, GPIO_INPUT);
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ret = ql_pin_set_func(99, 5); // set pin 98 to gpio8
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if (ret != QL_GPIO_SUCCESS)
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{
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LOGE("ql_pin_set_func 99 err ret=%d", ret);
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}
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ql_gpio_set_direction(GPIO_8, GPIO_OUTPUT);
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ret = ql_pin_set_func(100, 5); // set pin 95 to gpio12
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if (ret != QL_GPIO_SUCCESS)
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{
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LOGE("ql_pin_set_func 100 err ret=%d", ret);
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}
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ql_gpio_set_direction(GPIO_8, GPIO_OUTPUT);
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while (1)
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{
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ql_event_t event;
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ret = ql_event_wait(&event, 1000);
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if (ret == 0)
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{
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switch (event.id)
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{
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case BL0939_READ_TIMER:
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memcpy(spi_txbuf, bl0939_cmd, sizeof(bl0939_cmd));
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ret = spi_write_read(spi_no, spi_txbuf, spi_rxbuf, 36);
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if (ret == 0)
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{
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for (int ch = 0; ch < 3; ch++)
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{
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if (check_sum_ch(spi_rxbuf, spi_txbuf, 8 + ch * 12))
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{
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ac_ad_values[ch] = readUint24BE(spi_rxbuf, 8 + ch * 12);
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LOGI("channel : %d ac_ad_values: %d\n ", ch, ac_ad_values[ch]);
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gWordVar[AC_CURRENT_REG_ADDR + ch] = ac_ad_values[ch] * ac_current_coef[ch];
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}
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else
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{
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int value = readUint24BE(spi_rxbuf, 8 + ch * 12);
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LOGW("check bed ch: %d ac_ad_values: %d\n ", ch, value);
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}
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// ac_ad_values[ch] = readUint24BE(bl0939_rxbuf,8+ch*12);
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// ESP_LOGI(TAG, "channel : %d ac_ad_values: %d\n ", ch, ac_ad_values[ch]);
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}
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}
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else
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{
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LOGE("spi_write_read err ret=%d\r\n", ret);
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}
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gWordVar[ENC_VALUE_REG_ADDR] = enc_value & 0xffff;
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gWordVar[ENC_VALUE_REG_ADDR + 1] = enc_value >> 16;
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ql_LvlMode gpio_value9;
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ql_LvlMode gpio_value10;
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ql_gpio_get_level(GPIO_9, &gpio_value9);
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ql_gpio_get_level(GPIO_10, &gpio_value10);
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gWordVar[ENC_VALUE_REG_ADDR + 2] = gpio_value9 | (gpio_value10 << 1);
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break;
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}
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}
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else
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{
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LOGE("timer not work ??", ret);
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osiTimerStart(bl_timer, 20);
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}
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}
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}
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