203 lines
6.5 KiB
C
203 lines
6.5 KiB
C
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/** @file
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ql_pin_cfg.h
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@brief
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This file provides the definitions for ql pin cfg, and declares the API functions.
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*/
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/*================================================================
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Copyright (c) 2020 Quectel Wireless Solution, Co., Ltd. All Rights Reserved.
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Quectel Wireless Solution Proprietary and Confidential.
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=================================================================*/
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/*=================================================================
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EDIT HISTORY FOR MODULE
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This section contains comments describing changes made to the module.
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Notice that changes are listed in reverse chronological order.
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WHEN WHO WHAT, WHERE, WHY
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------------ ------- -------------------------------------------------------------------------------
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15/03/2021 Neo Init version
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=================================================================*/
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#ifndef QL_PIN_CFG_H
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#define QL_PIN_CFG_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdio.h>
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#include "ql_type.h"
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#include "ql_gpio.h"
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#include "ql_app_feature_config.h"
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#include "quec_pin_index.h"
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/*===========================================================================
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* Macro
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===========================================================================*/
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#define QUEC_PIN_NONE 0xff
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//different projects are changed into different corresponding relationships
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//for power demo
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#define QL_FUN_NUM_UART_2_CTS 3
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#define QL_FUN_NUM_UART_3_TXD 4
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//for ledcfg demo
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#ifdef CONFIG_QL_PROJECT_DEF_EG912U
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//EG912型号QUEC_PIN_CFG_MAX值统计为kernel使用pin脚，根据GNSS和负载开关宏控，会增加6个虚拟的pin脚，在APP侧不能使用
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#define QL_GPIO_PIN_MAX 45
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#else
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#define QL_GPIO_PIN_MAX QUEC_PIN_CFG_MAX
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#endif
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#define QL_PIN_NUM_KEYOUT_5 QUEC_PIN_DNAME_KEYOUT_5
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#define QL_PIN_GPIO1 126
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#define QL_PIN_GPIO1_FUNC_ZSP_CTS 3
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#define QL_PIN_FLASH_DATA2 79
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#define QL_PIN_FLASH_DATA2_FUNC_FLASH_SIO2 1
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#ifdef QL_APP_PROJECT_DEF_EC200U
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#define QL_PIN_NET_MODE 6
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#define QL_PIN_NET_MODE_FUNC_GPIO 4
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#define QL_GPIO_NET_MODE 22
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#define QL_PIN_SIM0_HOTPLUG 13
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#define QL_PIN_SIM0_HOTPLUG_FUNC_GPIO 0
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#define QL_GPIO_SIM0_HOTPLUG GPIO_4
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#elif defined QL_APP_PROJECT_DEF_EC600U
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#define QL_PIN_NET_MODE 52
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#define QL_PIN_NET_MODE_FUNC_GPIO 2
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#define QL_GPIO_NET_MODE 30
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#define QL_PIN_SIM0_HOTPLUG 9
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#define QL_PIN_SIM0_HOTPLUG_FUNC_GPIO 0
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#define QL_GPIO_SIM0_HOTPLUG GPIO_8
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#elif defined QL_APP_PROJECT_DEF_EG700U || defined QL_APP_PROJECT_DEF_EG070U
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#define QL_PIN_NET_MODE 81
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#define QL_PIN_NET_MODE_FUNC_GPIO 1
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#define QL_GPIO_NET_MODE 4
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#define QL_PIN_SIM0_HOTPLUG 22
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#define QL_PIN_SIM0_HOTPLUG_FUNC_GPIO 0
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#define QL_GPIO_SIM0_HOTPLUG GPIO_23
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#elif defined QL_APP_PROJECT_DEF_EG500U
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#define QL_PIN_NET_MODE 72
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#define QL_PIN_NET_MODE_FUNC_GPIO 2
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#define QL_GPIO_NET_MODE 30
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#define QL_PIN_SIM0_HOTPLUG 17
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#define QL_PIN_SIM0_HOTPLUG_FUNC_GPIO 0
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#define QL_GPIO_SIM0_HOTPLUG GPIO_5
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#elif defined QL_APP_PROJECT_DEF_EG915U
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#define QL_PIN_NET_MODE QUEC_PIN_NONE
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#define QL_PIN_NET_MODE_FUNC_GPIO QUEC_PIN_NONE
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#define QL_GPIO_NET_MODE QUEC_PIN_NONE
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#define QL_PIN_SIM0_HOTPLUG 42
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#define QL_PIN_SIM0_HOTPLUG_FUNC_GPIO 0
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#define QL_GPIO_SIM0_HOTPLUG GPIO_23
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#elif defined QL_APP_PROJECT_DEF_EC020U
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#define QL_PIN_NET_MODE 6
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#define QL_PIN_NET_MODE_FUNC_GPIO 4
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#define QL_GPIO_NET_MODE 19
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#define QL_PIN_SIM0_HOTPLUG 13
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#define QL_PIN_SIM0_HOTPLUG_FUNC_GPIO 0
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#define QL_GPIO_SIM0_HOTPLUG GPIO_14
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#elif defined QL_APP_PROJECT_DEF_EG912U
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#define QL_PIN_NET_MODE QUEC_PIN_NONE
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#define QL_PIN_NET_MODE_FUNC_GPIO QUEC_PIN_NONE
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#define QL_GPIO_NET_MODE QUEC_PIN_NONE
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#define QL_PIN_SIM0_HOTPLUG 42
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#define QL_PIN_SIM0_HOTPLUG_FUNC_GPIO 0
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#define QL_GPIO_SIM0_HOTPLUG GPIO_23
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#endif
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//for sdmmc demo
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#define QL_SDMMC_PIN_DET QUEC_PIN_DNAME_GPIO_15
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#define QL_PIN_SDMMC_CMD QUEC_PIN_DNAME_SDMMC1_CMD
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#define QL_PIN_SDMMC_DATA_0 QUEC_PIN_DNAME_SDMMC1_DATA_0
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#define QL_PIN_SDMMC_DATA_1 QUEC_PIN_DNAME_SDMMC1_DATA_1
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#define QL_PIN_SDMMC_DATA_2 QUEC_PIN_DNAME_SDMMC1_DATA_2
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#define QL_PIN_SDMMC_DATA_3 QUEC_PIN_DNAME_SDMMC1_DATA_3
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#define QL_PIN_SDMMC_CLK QUEC_PIN_DNAME_SDMMC1_CLK
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#define QL_PIN_SDMMC_MODE_FUNC 0
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#define QL_PIN_SDMMC_MODE_FUNC_GPIO 0
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//for gpio/gpio_int demo
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#define QL_TEST1_PIN_GPIO0 QUEC_PIN_DNAME_GPIO_0
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#define QL_TEST1_PIN_GPIO0_FUNC_GPIO 0
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#define QL_TEST1_PIN_GPIO0_FUNC_FLASH1_CLK 1
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#define QL_TEST1_PIN_GPIO1 QUEC_PIN_DNAME_GPIO_1
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#define QL_TEST1_PIN_GPIO1_FUNC_GPIO 0
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#define QL_TEST1_PIN_GPIO1_FUNC_FLASH1_CS 1
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#define QL_TEST2_PIN_GPIO0 QUEC_PIN_DNAME_SPI_LCD_SIO
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#define QL_TEST2_PIN_GPIO0_FUNC_GPIO 1
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#define QL_TEST2_PIN_GPIO0_FUNC_LCD_SIO 0
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#define QL_TEST2_PIN_GPIO1 QUEC_PIN_DNAME_SPI_LCD_SDC
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#define QL_TEST2_PIN_GPIO1_FUNC_GPIO 1
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#define QL_TEST2_PIN_GPIO1_FUNC_LCD_SDC 0
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//for rs485 demo
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#define QL_RS485_PIN_GPIO QUEC_PIN_DNAME_SDMMC1_DATA_1
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#define QL_RS485_PIN_GPIO_FUNC_GPIO 1
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#define QL_RS485_GPIO_NUM GPIO_26
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//for uart demo
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#define QL_UART2_TX_PIN QUEC_PIN_UART2_TXD
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#define QL_UART2_RX_PIN QUEC_PIN_UART2_RXD
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#ifdef QL_APP_PROJECT_DEF_EC200U
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#define QL_UART2_TX_FUNC 0x03
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#define QL_UART2_RX_FUNC 0x03
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#else
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#define QL_UART2_TX_FUNC 0x01
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#define QL_UART2_RX_FUNC 0x01
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#endif
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/*===========================================================================
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* Struct
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===========================================================================*/
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typedef struct
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{
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uint8_t pin_num;
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uint8_t default_func;
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uint8_t gpio_func;
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ql_GpioNum gpio_num;
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ql_GpioDir gpio_dir;
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ql_PullMode gpio_pull;
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ql_LvlMode gpio_lvl;
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} ql_pin_cfg_t;
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/*===========================================================================
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* Extern
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===========================================================================*/
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extern const ql_pin_cfg_t ql_pin_cfg_map[];
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#ifdef __cplusplus
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} /*"C" */
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#endif
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#endif /* QL_PIN_CFG_H */
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